1. Field of the Invention
The invention relates in general to a method of assembling chips, and more particular, to a method of assembling chips with an enhanced packaging yield.
2. Description of the Prior Art
In the modern information explosive society, electronic products are everywhere in our daily lives. Accompanied with the continuously developed electronic technology, more complex and more humanized products are updated every single moment. The exterior design of the electronic products is also driven by the trend for being light, thin, short and small. For example, in the field of semiconductor package, many high-density semiconductor package techniques have been developed, such as the system in a package, the flip chip (F/C) structure, and the ball grid array (BGA).
Normally, the pattern of the systemized package structure includes multiple chips packaged in an encapsulating material. Such package structure has the advantages of short interconnection between chips and greatly reduced volume for wiring layout. However, there is some difficulty in the fabrication process thereof. For example, when two flip chips are connected to each other, misalignment problem frequently occurs as shown in FIGS. 1 to 5, which illustrate the flip chip connecting process.
In FIG. 1, first and second flip chips 110, 130 are provided. The first flip chip 110 has a first chip 112 and a first bump 122. The first chip has several first terminals 114 exposed at the surface of the first chip 112. Each of the first bumps 122 is positioned on the corresponding first terminal 114. The first bumps 122 are in ball patterns. The second flip chip 130 includes a second chip 132 and multiple second bumps 143. The second flip chip 130 further has multiple second terminals 134 exposed at the surface of the second chip 132. Each of the second bumps 142 is located on the corresponding second terminal 134. The second bumps 142 have ball shape.
The first chip and the second chip are then connected to each other. The first bumps 122 are dipped with flux 150 as shown in FIG. 2. The first flip chip 110 is then turned up side down, such that each first bump 122 is aligned and pressed on one corresponding second bump 142. Meanwhile, the joint between the first bump 122 and the second bump 142 is covered with the flux 150 as shown in FIG. 3. As both the first and second bumps 122 and 142 are in ball shape, a sliding motion between the first and second bumps 122 and 142 is inevitable when the first bumps 122 are pressed on the second bumps 142. Therefore, a displacement or shift between the first and second bumps 122 and 142 is caused.
A reflow process is then performed allowing each first bump 122 and the corresponding second bump 142 melted to form a common connecting block 160, while the flux 150 flows to an external surface of the connecting block 160 to cover the connecting block 160 as shown in FIG. 4. In case that a serious sliding motion occurs for pressing the first bumps 122 on the second bumps 142, the neighboring blocks 160 may contact each other during the reflow process. A short circuit is thus caused to reduce the package yield.
After the reflow process, a solution (not shown) is applied to remove the residual flux 150 on the blocks 160 to form the structure as shown in FIG. 5.
In the above bump-connecting process, the height of the connecting blocks 160 is limited, such that the distance between the first and second chip 112 and 132 is too small. In the following glue dispensing or encapsulating process, the encapsulating material (not shown) can hardly flowing between the first and second chips 112 and 132, such that void is formed therebetween, and the reliability of the package is degraded.